The vast majority of these mainstream semiconductors are actually manufactured on something less than leading edge technologies. Analog devices, sensors, microcontrollers, optoelectronics, discretes, MEMS and a number of other semiconductor products comprise the largest markets in terms of semiconductor units.

In order to address the increased demand for mature processing capacity, manufacturing facilities can expand in two ways. In some cases, factories can increase unit output with marginal productivity increases and yields. However, many of these factories have already maximized equipment productivity and process yields. Such factories require additional equipment to increase wafer output. In addition, some higher volume products are able to benefit from an increase in wafer size, transitioning from 100mm to 150mm, or from 150mm wafers to 200mm wafers, thus creating new demand, refurbishment, servicing and repurposing opportunities for 150mm and 200mm capacity.

SEMI, the industry association serving the equipment and material supply chains for the microelectronic, display and photovoltaic industries, established a SEMI Special Interest Group — Secondary Equipment, Services and Technology Group (SESTG). The SESTG special interest group provides a worldwide focus for the secondary market – OEMs, equipment refurbishers, resellers, users, and service providers.

As part of its mission, SEMI/SESTG joined with Semico Research Corp. to embark on a research study to provide ongoing data and analysis that defines the secondary equipment, services and technology markets. Semico Research Corp. is a marketing and consulting research company founded in 1994 by a group of semiconductor industry experts who have improved the validity of semiconductor product forecasts via technology roadmaps in end-use markets.

This study collected information from a wide variety of market players around the world, both large and small, from dealers to refurbishers to OEMs to IDMs. We embarked on this study knowing that the semiconductor secondary equipment market is complex and disaggregated. Needless to say, gathering and analyzing the data was challenging, however the results are interesting and are expected to play a dynamic and significant role for this market segment.

Complex, disaggregated markets are inefficient. Information is not consistently available causing duplication of effort, disparate pricing, variation in quality and often unsatisfactory experiences. This study attempts to shed some light on this multifaceted market. The report includes data on the size of the market, with breakouts by vendor type, regions and type of equipment. Reaching $6 billion, secondary equipment sales represent approximately 13% of total semiconductor equipment sales and increased over 77% in 2010 over 2009.

Although the semiconductor industry transitioned from 100mm wafers to 125mm wafers to 150mm wafers to 200mm wafers, the transition from 200mm to 300mm wafers marked the first time that a significant market for secondary equipment emerged. Brokers, dealers, refurbishers and other IDMs entered this market to take advantage of a need that this industry never experienced before. Currently the largest equipment vendors sell less than 50% of the secondary equipment. Interviews with IDMs revealed that most companies prefer to purchase equipment that is ready to install and yet the market is still supported by a variety of players in the supply chain.

In most cases, as markets mature, clear winners emerge, eliminating a number of inefficient players. That is not the case with the secondary equipment market, yet.

For more information click here http://semico.com/studies/category.asp?id=13#1392 or call Sam Caldwell at 602-214-9697.

Joanne Itow, Managing Director

Just like CMOS image sensors filled the mature, unused fab capacity in 2003, MEMS is now expected to be the fab filler for this decade.  CMOS image sensors experienced quick adoption as it penetrated the consumer digital camera market but it grew from millions of units to billions when almost every cell phone integrated a camera into its handset.  That is one example of a success story.  But what about RFID?  RFID was suppose to be on every retail product tracking sales and inventory at Walmart and on every passport and drivers license for personal identification and security.  Those units have not materialized.  

MEMS has the potential to be much more than just a fab-filler.  For years MEMS have been used in hard disc drives and airbags for automotive markets.  They are now making inroads into other safety and engine control sensors in automotive applications.  MEMS are now gaining more recognition as they make their way into consumer devices even beyond smart phones and game controllers. 

Basic MEMS technology may not require rocket science but the potential to move into more consumer applications is driving a whole new growth segment for MEMS.  Last week Semico was briefed by a company named Coventor, an EDA tool developer with a unique niche.  Addressing the consumer need for quick time to market and integrating CMOS IC design technology, Coventor offers software suites that analyze the whole system.  Coventor has teamed up with Cadence to provide tools that allow the IC and MEMS designers to simulate their designs in a common environment.  This is more important as different MEMS functions are being integrated together.  Coventor points out that simulations must include more of the system than individual blocks.  There is no standard methodology in the industry for developing an integrated MEMS IC.

New EDA tools and more fab capacity from the mainstream foundries such as GLOBALFOUNDRIES and TSMC will provide the right conditions for broader adoption of MEMS in high volume applications.  Will this be enough to propel MEMS into the billions of units?  The MEMS Executive Congress is just around the corner and there’s already quite a buzz around all the new activities targeted at MEMS applications. 

Joanne Itow, Managing Director

Tony Massimini, Chief of Technology

 Panasonic developed their process with Renesas Electronics Corp. based on a research program with IMEC.  Panasonic uses a hafnium based high-k dielectric with their metal gate electrodes.  Assuming this chip is being manufactured in Panasonic’s Uozu fab in Japan, that means Panasonic is the second company to mass produce and ship a 32nm HKMG product. Of course, Intel was the first.  AMD has manufactured chips at GLOBALFOUNDRIES using their 32nm gate-first HKMG technology but is not expected to begin shipping product until 1H 2011. 

Who would have guessed that the industry’s most advanced process technology would be used to mass produce chips that would be shipped this month for a consumer video player?  I do love my videos but does a Blu-ray 3D Disc^TM really require semiconductor chip technology that is considered bleeding edge?  This is most likely a MOS Special Purpose Logic chip.  Panasonic says this technology is enabling them to improve transistor performance by up to 40% while cutting power consumption by 40%. 

The adoption of gate-first for a consumer application does make sense.  Gate-first HKMG is touted as the solution for applications in fast-growing markets and is suppose to be less expensive and easier to implement with fewer process steps.    

Anyone who said that technology development and adoption is slowing better take another look at what is selling in Best Buy this holiday season.  Semico is expecting another 32nm/28nm product announcement using gate-last sometime in October.  If I were to start keeping score, I think gate-first and gate-last are still tied in this playoff series. 

Joanne Itow

Managing Director

The ITRS (International Technology Roadmap for Semiconductors) has outlined a transition path for us that was adopted by a majority of manufacturers. Most advanced logic products use copper, and now high-k, metal gate. A majority of companies with advanced manufacturing capabilities have moved to immersion lithography. Many processes and materials had a way of becoming accepted as standard.

Moving into the next generation process technology, semiconductor manufacturers, both fabless and IDM, have to make a number of significant manufacturing decisions which could impact their product’s market applications and the ability to deliver timely, future products. The semiconductor manufacturing decision involves more than just a process node or cost of ownership. Manufacturing technology is becoming a major decision point with numerous options.

Two years ago TSMC came out with their 40nm node. What used to be a half node is now a sweet spot. Now we have fully developed processes at 45nm, 40nm, 32nm, soon 28nm and 22nm.
Which node do you use for your next design? Companies are even skipping a generation altogether. For their high performance product lines, Freescale went from 90nm directly to 45nm/40nm.

At 32nm/28nm do you go with gate-first or gate-last? Samsung claimed bragging rights as the first foundry with a qualified 32nm gate-first process. Proponents of gate-first believe it’s a simpler solution. Intel and TSMC are using gate-last or replacement metal gate. Intel started production on their 32nm replacement metal gate process last year. Proponents of gate-last plan on using the technology for future generations and believe that gate-first is a “one hit wonder”, good for only one generation.

Admittedly there has always been a difference between the SOI wafer proponents and the non-SOI users. The anti-SOI wafer camp continues to search for ways to avoid the use of SOI wafers. At the VLSI Symposium in June, Intel presented an update on their floating body cell technology. Their solution requires several steps to add an insulative BOX, only where necessary, hence the term localized SOI. Intel claims the result is a customized ultrathin SOI providing optimized back-gate and body doping. Why go through these extra steps instead of using an SOI wafer? Currently IBM’s R&D SOI process requires a step to thin existing SOI wafers. But SOITEC’s roadmap does include a 10-20nm ultrathin wafer expected to be available for 22nm production and beyond.

Certainly, there is always more than one way to solve a problem. But can the industry afford to run so many different processes? Will we find that one process truly is better than the other? Two years ago I didn’t think it was feasible for TSMC to buck the trend with their 40nm process. Nonetheless, they are a leader and when they rolled out 40nm, other foundries felt they had to follow.

Semiconductor manufacturers have encountered many decision points when it comes to technology options. In the past, companies would eventually converge onto similar paths in terms of materials and processes because the best solution had a way of rising to the top. At a time when the industry is under pressure to reduce costs and time-to-market we seem to be driving ourselves to more complex and diverse ways to reach the same goal. Choosing your foundry partner involves a lot more than just wafer price. Could the selection of a particular process technology actually make or break a product line? It appears we are following the advice of Yogi Berra: When you get to a fork in the road, take it.

Joanne Itow,
Managing Director

The industry cannot stagnate at the existing 300mm wafer technology. Consumer demands for more memory will push NAND and DRAM to ever increasing product densities and increased unit volumes. Logic products will continue to move up the performance curve while offering more features in a system-on-chip or high performance multi-core product. The ability to produce chips on a more economical manufacturing process is good for the overall industry’s future. It’s the availability of low cost memory and high performance and/or low power processors that enables the creation of new applications, increasing demand for electronic goods and more semiconductors, a cycle that keeps our industry ticking.

And don’t forget, it’s the availability of mature capacity that enables a plethora of new features. When DRAM vendors moved to 300mm wafers, they used their old 200mm capacity to produce cost-effective CMOS image sensors. LED, medical applications and smart grid are being enabled because of efficient 200mm capacity which is available as advanced products move on.

In order to meet our next generation technology demands, the industry will have to find a revolutionary solution. Whether it is 450mm wafers or not, the solution will most likely be expensive and disruptive. But every time an industry executive says we can’t afford the R&D, it sends a discouraging message to all the young, creative engineers: the semiconductor industry is stagnant, protecting profit margins instead of forging new markets.

Competitive markets are designed to weed out the poor performers, but we are weeding out the risk-takers and we’re no longer attracting the best of the young, innovative entrepreneurs. We all need to be sending a positive message that the magic in the black box, whether it is a cell phone or an iPad, starts in the manufacturing of the semiconductor chips.

It’s time for the industry to quit viewing semiconductor technology at the end of a long journey. We haven’t exhausted our technology option! Let’s get back to an innovative mindset!

Joanne Itow, Managing Director

Memory is one of those categories that when capacity is squeezed manufacturers find ways to improve yields and/or switch to higher densities. DRAM units are expected to grow by 17%, while wafer demand will only grow by 15%. NAND units are expected to grow by almost 16%, while wafer demand will only increase by 13.5%.

Semico data shows that the biggest area for silicon savings in 2010 is in the communication Micro Logic categories. Units are expected to grow by almost 27%, while silicon demand will only grow by 19%. More efficient production on 45nm/40nm is one of the main reasons for the more efficient use of silicon.

In addition to the tight capacity situation, silicon usage continues to be influenced by the transition to more advanced technology. Intel introduced 32nm production in late 2009. In 2009, almost 28% of all silicon was processed on 65nm technology or finer. By 2014 over 40% of all wafers will require technologies in that category.

More detailed wafer demand forecast information can be found in Semico Research’s latest release Semico Quarterly Wafer Demand Data and the Wafer Demand Summary and Assumptions Q1’10. To see more information on this data go to http://tinyurl.com/28kxus8

The addition of other process geometries and other foundries’ processes will further increase interest in doing designs on SOI wafers. The entire process of having major players in the semiconductor, IP and EDA markets come together to collaborate on developing this ecosystem validates the proposition that SOI can bring greater long term benefits than by just continuing to use bulk CMOS

In general, creating a comprehensive ecosystem around IP aimed at use in SOI designs will be beneficial to the industry in the long run. However, in this case, the specific value of these announcements is the willingness of manufacturers and EDA companies to step up and go to bat for SOI regarding the cost benefits of using SOI over bulk CMOS. This seems like it could have the biggest short and long term benefit to the SOI camp. Just educating people on the fact that when you take into consideration the total cost to create designs on SOI, the increase in performance and decrease in power consumption, and not focus on just the actual wafer costs, the overall, long term benefits will be much greater. This will jump start people going in the SOI direction more than by just having a complete IP ecosystem available. The ecosystem will help the people who are already predisposed to favor SOI wafer for their next design. The education of those not predisposed towards using SOI today will have a larger impact since there are many more companies in this last group. Just getting some of these ‘hold-outs’ into the SOI camp will have a bigger effect over the long term.

Richard Wawrzyniak
Senior Analyst ASIc/SOC

On March 17th, 2010, SEMI released its 2009 semiconductor material market statistics.  While the headline pegged worldwide semiconductor material sales at $34.6 billion, that was reportedly a 19% decline in sales compared to 2008.

Although SEMI stated that was not as bad as the 26% decline suffered by material suppliers in the devastating 2001 down cycle, the numbers aren’t easy to swallow.

Table 1:  Semiconductor Revenues, Units, Wafers, Materials

Source:  SEMI, SIA/WSTS and Semico Research Corp.

SIA/WSTS reports that total semiconductor units dropped by 5.6%.  Semico Research’s analysis determined wafer demand only dropped by 2.7%.  How did the materials going into the making of these chips and wafers decline by 19%?  Even total semiconductor revenues only declined by 9%.

Here are some possible reasons.

1. Semiconductor manufacturers      had a stockpile of inventory and worked those down
2. Semiconductor manufacturers      were able to reduce material consumption.
3. Material prices declined.

In today’s just-in-time environment, Semico does not believe that manufacturers stockpile.  The draw down of inventories could not have been a significant contributor to the decline in material sales.

Did productivity improvements cut material inputs at double digit rates?  Productivity improvements in material were certainly likely.  But once again, we would be surprised if manufacturers reduced material inputs by that much.

Did suppliers cut material prices just to sell product?  We do know that material demand recovered by the second half of the year and in some cases, so did pricing.  In fact, some materials actually increased in price, such as gold. But total silicon wafer sales for semiconductor production was reported at $6.7 billion in 2009 compared to $11.4 billion in 2008, a 41% drop.  Silicon is approximately 47.1% of the total wafer manufacturing material (not including packaging materials) in 2008 and 37% in 2009.  That’s a significant drop in the cost attributable to the silicon wafer.

Table 2:  Silicon as a Percent of Wafer Manufacturing Materials

Note:  Wafer manufacturing materials equals total materials minus packaging materials.
Source:  SEMI, Semico Research Corp.

So if total material costs really did decline by 18.5%, semiconductor manufacturers should have experienced some nice margins.  Is this true?  We should see evidence of this in foundry margins.   This could also mean lots of room for chip price reductions in the coming year.  As Walden Rhines, CEO Mentor Graphics pointed out at the 2010 Semico Outlook event, lower ASPs will spur another round of innovative applications for the efficient and cost effective transistors.

Their copper and leading edge process drives lower voltages and higher reliability.  Micron’s goal is to be the lowest-cost manufacturer.

The ventures with Intel and Inotera provide 50% of both DRAM and NAND, which is a great strategic move.

Looking at fab tools, lead times for litho tools have extended to 10-12 months.  Micron claims that they have slots for the tools that they need; however, the overall industry may be limited.

One tool per month through 2011 at Inotera.  Inotera will ramp 50nm in 2010, with 42nm starting Q4 2010.  Moving to 42nm will bring a huge productivity improvement at Inotera, and will cost $2 billion.

On top of this, Micron is generating substantial cash.

– Posted from Micron’s winter analyst meeting